S3C2440A

Cao ốc A Nguyễn Kim, Phường 7, Quận 10, Tp Hồ Chí Minh

nguyenthaibinh04@gmail.com

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S3C2440A

Mã SP:

MUD000A432
Giá:

293,000^VND
Lượt xem:

2852
Số lượng:
Mô tả:

MCU ARM9, 400MHz, 289-FBGA, Samsung

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This user’s manual describes SAMSUNG's S3C2440A 16/32-bit RISC microprocessor. SAMSUNG’s S3C2440A is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2440A includes the following components. The S3C2440A is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier. Its lowpower, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA). The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length. By providing a complete set of common system peripherals, the S3C2440A minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include:

Around 1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB DCache/

MMU

External memory controller (SDRAM Control and Chip Select logic)
LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA
4-ch DMA controllers with external request pins
3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)
2-ch SPls
IIC bus interface (multi-master support)
IIS Audio CODEC interface
AC’97 CODEC interface
SD Host interface version 1.0 & MMC Protocol version 2.11 compatible
2-ch USB Host controller / 1-ch USB Device controller (ver 1.1)
4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer
8-ch 10-bit ADC and Touch screen interface
RTC with calendar function
Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for scaling)
130 General Purpose I/O ports / 24-ch external interrupt source
Power control: Normal, Slow, Idle and Sleep mode
On-chip clock generator with PLL

Architecture

Integrated system for hand-held devices and general embedded applications.
16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core.
Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux.
Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance.
ARM920T CPU core supports the ARM debug architecture.
Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB).

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